#!/usr/bin/perl -w

#    Read AMD64 CPU northbridge registers.
#    Copyright (C) 2005  Jaakko Hyvätti
#
#    This program is free software; you can redistribute it and/or modify
#    it under the terms of the GNU General Public License as published by
#    the Free Software Foundation; either version 2 of the License, or
#    (at your option) any later version.
#
#    This program is distributed in the hope that it will be useful,
#    but WITHOUT ANY WARRANTY; without even the implied warranty of
#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
#    GNU General Public License for more details.
#
#    You should have received a copy of the GNU General Public License
#    along with this program; if not, write to the Free Software Foundation,
#    Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
#
# The author may be contacted at:
#
# Email: Jaakko.Hyvatti@iki.fi
# URL:   http://www.iki.fi/hyvatti/
# Phone: +358 40 5011222
# VOIP:  <sip:238812@fwd.pulver.com>
#
# Please send any suggestions, bug reports, success stories etc. to the
# Email address above.
#

#
# See AMD document 26094.PDF for further information.
#

use strict;

my @regs = (
# Function 0
#Offset Register Name                             Reset      Access Description
0x00, "Device ID", 16, "Vendor ID (AMD)", 16, 0x11001022, "RO", "page 31",
                    
0x04, "Status", 16, "Command", 16, 0x00100000, "RO", "page 32",
0x08, "Base Class Code", 8, "Subclass Code", 8, "Programming Interface", 8, "Revision ID", 8, 0x06000000, "RO", "page 32",
0x0C, "BIST", 8, "Header Type", 8, "Latency Timer", 8, "Cache Line Size", 8, 0x00800000, "RO", "page 33",
0x10, "Base Address 0", 32,                                  0x00000000, "RO", "",
0x14, "Base Address 1", 32, 0x00000000, "RO", "",
0x18, "Base Address 2", 32, 0x00000000, "RO", "",
0x1C, "Base Address 3", 32, 0x00000000, "RO", "",
0x20, "Base Address 4", 32, 0x00000000, "RO", "",
0x24, "Base Address 5", 32, 0x00000000, "RO", "",
0x28, "Card Bus CIS Pointer", 32, 0x00000000, "RO", "",
0x2C, "Sub-System ID", 16, "Sub-System Vendor ID", 16,  0x00000000, "RO", "",
0x30, "ROM Base Address", 32, 0x00000000, "RO", "",
0x34, "reserved", 24, "Capabilities Pointer", 8, "", "RO", "page 33",
0x38, "reserved", 32, 0x00000000, "RO", "",
0x3C, "Max Latency", 8, "Min GNT", 8, "Int Pin", 8, "Int Line", 8, 0x00000000, "RO", "",
0x40, "Routing Table Node 0", 32,                           0x00010101, "RW", "page 34",
0x44, "Routing Table Node 1", 32,                            0x00010101, "RW", "page 34",
0x48, "Routing Table Node 2", 32,                            0x00010101, "RW", "page 34",
0x4C, "Routing Table Node 3", 32,                            0x00010101, "RW", "page 34",
0x50, "Routing Table Node 4", 32,                            0x00010101, "RW", "page 34",
0x54, "Routing Table Node 5", 32,                            0x00010101, "RW", "page 34",
0x58, "Routing Table Node 6", 32,                            0x00010101, "RW", "page 34",
0x5C, "Routing Table Node 7", 32,                            0x00010101, "RW", "page 34",
0x60, "reserved", 12, "CPU Count", 4, "reserved", 1, "Lock Controller Node ID", 3, "reserved", 1, "HT I/O Hub Node ID", 3, "reserved", 1, "Node Count", 3, "reserved", 1, "Node Id", 3,                                         0x00000000, "RW", "page 35",
0x64, "reserved", 22, "HT I/O Hub Link ID", 2, "Host Bridge Unit ID", 2, "Memory Controller Unit ID", 2, "CPU1 Unit ID", 2, "CPU0 Unit ID", 2,                                        0x000000E4, "RW", "page 37",
0x68, "HyperTransport TM Transaction Control", 32,           0x0F000000, "RW", "page 38",
0x6C, "HyperTransport TM Initialization Control", 32,        "",  "RW", "page 42",
0x80, "LDT0 Capabilities", 32,                               "",  "RO", "page 44",
0x84, "LDT0 Link Control", 32,                               0x00110000, "RW", "page 45",
0x88, "LDT0 Frequency/Revision", 32,                         "",  "RW", "page 49",
0x8C, "LDT0 Feature Capability", 32,                         0x00000002, "RO", "page 50",
0x90, "LDT0 Buffer Count", 32,                               "",  "RW", "page 51",
0x94, "LDT0 Bus Number", 32,                                 0x00000000, "RW", "page 53",
0x98, "LDT0 Type", 32,                                       "",  "RO", "page 53",
0xA0, "LDT1 Capabilities", 32,                                "",  "RO", "page 44",
0xA4, "LDT1 Link Control", 32,                               0x00110000, "RW", "page 45",
0xA8, "LDT1 Frequency/Revision", 32, "", "RW", "page 49",
0xAC, "LDT1 Feature Capability", 32,  0x00000002, "RO", "page 50",
0xB0, "LDT1 Buffer Count", 32, "", "RW", "page 51",
0xB4, "LDT1 Bus Number", 32,         0x00000000, "RW", "page 53",
0xB8, "LDT1 Type", 32, "", "RO", "page 53",
0xC0, "LDT2 Capabilities", 32, "", "RO", "page 44",
0xC4, "LDT2 Link Control", 32,       0x00110000, "RW", "page 45",
0xC8, "LDT2 Frequency/Revision", 32, "", "RW", "page 49",
0xCC, "LDT2 Feature Capability", 32,  0x00000002, "RO", "page 50",
0xD0, "LDT2 Buffer Count", 32, "", "RW", "page 51",
0xD4, "LDT2 Bus Number", 32,         0x00000000, "RW", "page 53",
0xD8, "LDT2 Type", 32,               "", "RO", "page 53",

# Function 1

0x00, "Device ID", 16, "Vendor ID (AMD)", 16, 0x11001022, "RO", "page 31",
                    
0x04, "Status", 16, "Command", 16, 0x00100000, "RO", "page 32",
0x08, "Base Class Code", 8, "Subclass Code", 8, "Programming Interface", 8, "Revision ID", 8, 0x06000000, "RO", "page 32",
0x0C, "BIST", 8, "Header Type", 8, "Latency Timer", 8, "Cache Line Size", 8, 0x00800000, "RO", "page 33",
0x10, "Base Address 0", 32,                                  0x00000000, "RO", "",
0x14, "Base Address 1", 32, 0x00000000, "RO", "",
0x18, "Base Address 2", 32, 0x00000000, "RO", "",
0x1C, "Base Address 3", 32, 0x00000000, "RO", "",
0x20, "Base Address 4", 32, 0x00000000, "RO", "",
0x24, "Base Address 5", 32, 0x00000000, "RO", "",
0x28, "Card Bus CIS Pointer", 32, 0x00000000, "RO", "",
0x2C, "Sub-System ID", 16, "Sub-System Vendor ID", 16,  0x00000000, "RO", "",
0x30, "ROM Base Address", 32, 0x00000000, "RO", "",
0x34, "Capabilities", 32, 0x00000000, "RO", "",
0x38, "reserved", 32, 0x00000000, "RO", "",
0x3C, "Max Latency", 8, "Min GNT", 8, "Int Pin", 8, "Int Line", 8, 0x00000000, "RO", "",

0x40, "DRAM Base 0", 16, "reserved", 5, "Interleave Enable", 3, "reserved", 6, "Write Enable", 1, "Read Enable", 1,  "", "RW", "page 59",
0x44, "DRAM Limit 0", 16, "reserved", 5, "Interleave Select", 3, "reserved", 5, "Destination Node ID", 3,  "", "RW", "page 60",
0x48, "DRAM Base 1", 16, "reserved", 5, "Interleave Enable", 3, "reserved", 6, "Write Enable", 1, "Read Enable", 1,  "", "RW", "page 59",
0x4C, "DRAM Limit 1", 16, "reserved", 5, "Interleave Select", 3, "reserved", 5, "Destination Node ID", 3,  "", "RW", "page 60",
0x50, "DRAM Base 2", 16, "reserved", 5, "Interleave Enable", 3, "reserved", 6, "Write Enable", 1, "Read Enable", 1,  "", "RW", "page 59",
0x54, "DRAM Limit 2", 16, "reserved", 5, "Interleave Select", 3, "reserved", 5, "Destination Node ID", 3,  "", "RW", "page 60",
0x58, "DRAM Base 3", 16, "reserved", 5, "Interleave Enable", 3, "reserved", 6, "Write Enable", 1, "Read Enable", 1,  "", "RW", "page 59",
0x5C, "DRAM Limit 3", 16, "reserved", 5, "Interleave Select", 3, "reserved", 5, "Destination Node ID", 3,  "", "RW", "page 60",
0x60, "DRAM Base 4", 16, "reserved", 5, "Interleave Enable", 3, "reserved", 6, "Write Enable", 1, "Read Enable", 1,                "", "RW", "page 59",
0x64, "DRAM Limit 4", 16, "reserved", 5, "Interleave Select", 3, "reserved", 5, "Destination Node ID", 3,               "", "RW", "page 60",
0x68, "DRAM Base 5", 16, "reserved", 5, "Interleave Enable", 3, "reserved", 6, "Write Enable", 1, "Read Enable", 1,                "", "RW", "page 59",
0x6C, "DRAM Limit 5", 16, "reserved", 5, "Interleave Select", 3, "reserved", 5, "Destination Node ID", 3,               "", "RW", "page 60",
0x70, "DRAM Base 6", 16, "reserved", 5, "Interleave Enable", 3, "reserved", 6, "Write Enable", 1, "Read Enable", 1,                "", "RW", "page 59",
0x74, "DRAM Limit 6", 16, "reserved", 5, "Interleave Select", 3, "reserved", 5, "Destination Node ID", 3,               "", "RW", "page 60",
0x78, "DRAM Base 7", 16, "reserved", 5, "Interleave Enable", 3, "reserved", 6, "Write Enable", 1, "Read Enable", 1,                "", "RW", "page 59",
0x7C, "DRAM Limit 7", 16, "reserved", 5, "Interleave Select", 3, "reserved", 5, "Destination Node ID", 3,               "", "RW", "page 60",
0x80, "Memory-Mapped I/O Base 0", 24, "reserved", 4, "Lock", 1, "CPU Disable", 1, "Write Enable", 1, "Read Enable", 1, "", "RW", "page 62",
0x84, "Memory-Mapped I/O Limit 0", 24, "Non-Posted", 1, "reserved", 1, "Destination Link ID", 2, "reserved", 1, "Destination Node ID", 3, "", "RW", "page 63",
0x88, "Memory-Mapped I/O Base 1", 24, "reserved", 4, "Lock", 1, "CPU Disable", 1, "Write Enable", 1, "Read Enable", 1, "", "RW", "page 62",
0x8C, "Memory-Mapped I/O Limit 1", 24, "Non-Posted", 1, "reserved", 1, "Destination Link ID", 2, "reserved", 1, "Destination Node ID", 3, "", "RW", "page 63",
0x90, "Memory-Mapped I/O Base 2", 24, "reserved", 4, "Lock", 1, "CPU Disable", 1, "Write Enable", 1, "Read Enable", 1, "", "RW", "page 62",
0x94, "Memory-Mapped I/O Limit 2", 24, "Non-Posted", 1, "reserved", 1, "Destination Link ID", 2, "reserved", 1, "Destination Node ID", 3, "", "RW", "page 63",
0x98, "Memory-Mapped I/O Base 3", 24, "reserved", 4, "Lock", 1, "CPU Disable", 1, "Write Enable", 1, "Read Enable", 1, "", "RW", "page 62",
0x9C, "Memory-Mapped I/O Limit 3", 24, "Non-Posted", 1, "reserved", 1, "Destination Link ID", 2, "reserved", 1, "Destination Node ID", 3, "", "RW", "page 63",
0xA0, "Memory-Mapped I/O Base 4", 24, "reserved", 4, "Lock", 1, "CPU Disable", 1, "Write Enable", 1, "Read Enable", 1, "", "RW", "page 62",
0xA4, "Memory-Mapped I/O Limit 4", 24, "Non-Posted", 1, "reserved", 1, "Destination Link ID", 2, "reserved", 1, "Destination Node ID", 3, "", "RW", "page 63",
0xA8, "Memory-Mapped I/O Base 5", 24, "reserved", 4, "Lock", 1, "CPU Disable", 1, "Write Enable", 1, "Read Enable", 1, "", "RW", "page 62",
0xAC, "Memory-Mapped I/O Limit 5", 24, "Non-Posted", 1, "reserved", 1, "Destination Link ID", 2, "reserved", 1, "Destination Node ID", 3, "", "RW", "page 63",
0xB0, "Memory-Mapped I/O Base 6", 24, "reserved", 4, "Lock", 1, "CPU Disable", 1, "Write Enable", 1, "Read Enable", 1, "", "RW", "page 62",
0xB4, "Memory-Mapped I/O Limit 6", 24, "Non-Posted", 1, "reserved", 1, "Destination Link ID", 2, "reserved", 1, "Destination Node ID", 3, "", "RW", "page 63",
0xB8, "Memory-Mapped I/O Base 7", 24, "reserved", 4, "Lock", 1, "CPU Disable", 1, "Write Enable", 1, "Read Enable", 1, "", "RW", "page 62",
0xBC, "Memory-Mapped I/O Limit 7", 24, "Non-Posted", 1, "reserved", 1, "Destination Link ID", 2, "reserved", 1, "Destination Node ID", 3, "", "RW", "page 63",
0xC0, "PCI I/O Base 0", 32,            "", "RW", "page 64",
0xC4, "PCI I/O Limit 0", 32,           "", "RW", "page 65",
0xC8, "PCI I/O Base 1", 32,            "", "RW", "page 64",
0xCC, "PCI I/O Limit 1", 32,           "", "RW", "page 65",
0xD0, "PCI I/O Base 2", 32,            "", "RW", "page 64",
0xD4, "PCI I/O Limit 2", 32,           "", "RW", "page 65",
0xD8, "PCI I/O Base 3", 32,            "", "RW", "page 64",
0xDC, "PCI I/O Limit 3", 32,           "", "RW", "page 65",
0xE0, "Configuration Base and Limit 0", 32, "", "RW", "page 66",
0xE4, "Configuration Base and Limit 1", 32, "", "RW", "page 66",
0xE8, "Configuration Base and Limit 2", 32, "", "RW", "page 66",
0xEC, "Configuration Base and Limit 3", 32, "", "RW", "page 66",

# Function 2

0x00, "Device ID", 16, "Vendor ID (AMD)", 16, 0x11001022, "RO", "page 31",
                    
0x04, "Status", 16, "Command", 16, 0x00100000, "RO", "page 32",
0x08, "Base Class Code", 8, "Subclass Code", 8, "Programming Interface", 8, "Revision ID", 8, 0x06000000, "RO", "page 32",
0x0C, "BIST", 8, "Header Type", 8, "Latency Timer", 8, "Cache Line Size", 8, 0x00800000, "RO", "page 33",
0x10, "Base Address 0", 32,                                  0x00000000, "RO", "",
0x14, "Base Address 1", 32, 0x00000000, "RO", "",
0x18, "Base Address 2", 32, 0x00000000, "RO", "",
0x1C, "Base Address 3", 32, 0x00000000, "RO", "",
0x20, "Base Address 4", 32, 0x00000000, "RO", "",
0x24, "Base Address 5", 32, 0x00000000, "RO", "",
0x28, "Card Bus CIS Pointer", 32, 0x00000000, "RO", "",
0x2C, "Sub-System ID", 16, "Sub-System Vendor ID", 16,  0x00000000, "RO", "",
0x30, "ROM Base Address", 32, 0x00000000, "RO", "",
0x34, "Capabilities", 32, 0x00000000, "RO", "",
0x38, "reserved", 32, 0x00000000, "RO", "",
0x3C, "Max Latency", 8, "Min GNT", 8, "Int Pin", 8, "Int Line", 8, 0x00000000, "RO", "",

0x40, "DRAM CS Base 0", 31, "Enable", 1,             0x00000000, "RW", "page 71",
0x44, "DRAM CS Base 1", 31, "Enable", 1,             0x00000000, "RW", "page 71",
0x48, "DRAM CS Base 2", 31, "Enable", 1,             0x00000000, "RW", "page 71",
0x4C, "DRAM CS Base 3", 31, "Enable", 1,             0x00000000, "RW", "page 71",
0x50, "DRAM CS Base 4", 31, "Enable", 1,             0x00000000, "RW", "page 71",
0x54, "DRAM CS Base 5", 31, "Enable", 1,             0x00000000, "RW", "page 71",
0x58, "DRAM CS Base 6", 31, "Enable", 1,             0x00000000, "RW", "page 71",
0x5C, "DRAM CS Base 7", 31, "Enable", 1,             0x00000000, "RW", "page 71",
0x60, "DRAM CS Mask 0", 32,             0x00000000, "RW", "page 74",
0x64, "DRAM CS Mask 1", 32,             0x00000000, "RW", "page 74",
0x68, "DRAM CS Mask 2", 32,             0x00000000, "RW", "page 74",
0x6C, "DRAM CS Mask 3", 32,             0x00000000, "RW", "page 74",
0x70, "DRAM CS Mask 4", 32,             0x00000000, "RW", "page 74",
0x74, "DRAM CS Mask 5", 32,             0x00000000, "RW", "page 74",
0x78, "DRAM CS Mask 6", 32,             0x00000000, "RW", "page 74",
0x7C, "DRAM CS Mask 7", 32,             0x00000000, "RW", "page 74",
0x80,
#DRAM Bank Address Mapping
"reserved", 17, "CS7/6", 3, "reserved", 1, "CS5/4", 3, "reserved", 1, "CS3/2", 3, "reserved", 1, "CS1/0", 3,  0x00000000, "RW", "page 75",
0x88, "reserved", 3, "Write Recovery Time", 1, "reserved", 1, "Row Precharge Time", 3, "Minimum RAS# Active Time", 4, "reserved", 1, "Active-to-active (RAS#-to-RAS#) Delay", 3, "reserved", 1, "RAS#-active to CAS#-read/write Delay", 3, "Row Refresh Cycle Time", 4, "Row Cycle Time", 4, "reserved", 1, "CAS# Latency", 3, 0x00000000, "RW", "page 81",
0x8C, "reserved", 9, "Write CAS Latency", 3, "reserved", 7, "Refresh Rate", 5, "reserved", 1, "Read-to-Write Delay", 3, "reserved", 3, "Write-to-Read Delay", 1,          0x00000000, "RW", "page 83",
0x90, "reserved", 3, "Enable 2T Timing", 1, "Bypass Max", 3, "Disable DRAM Receivers", 1, "x4DIMMS", 4, "Enable 32-Byte Granularity", 1, "Unbuffered DIMMs", 1, "DIMM ECC Enable", 1, "128-Bit/64-Bit", 1, "Read/Write Queue Bypass Count", 2, "Self-Refresh Status", 1, "Exit Self-Refresh", 1, "Memory Clear Status", 1, "DRAM Enable", 1, "reserved", 1, "DramInit", 1, "reserved", 4, "Disable DQS Hysteresis", 1, "QFC_EN Enable", 1, "D_DRV", 1, "DLL Disable", 1,   0x00000000, "RW", "page 85",
0x94,
"reserved", 2,
"Memory Clock 3 Enabled", 1,
"Memory Clock 2 Enabled", 1,
"Memory Clock 1 Enabled", 1,
"Memory Clock 0 Enabled", 1,
"Memory Clock Ratio Valid", 1,
"reserved", 2,
"DRAM MEMCLK Frequency", 3,
"Dynamic Idle Cycle Counter Enable", 1,
"Idle Cycle Limit", 3,
"reserved", 4,
"Read Preamble", 4,
"reserved", 4,
"Maximum Asynchronous Latency", 4,
    0x00000000, "RW", "page 88",
0x98, "reserved", 6, "Adjust Faster", 1, "Adjust Slower", 1, "Delay Line Adjust", 8, "reserved", 16,        0x00000000, "RW", "page 91",
0x9C, "Scratch Register", 32,           0x00000000, "RW", "page 91",

# Function 3

0x00, "Device ID", 16, "Vendor ID (AMD)", 16, 0x11001022, "RO", "page 31",
                    
0x04, "Status", 16, "Command", 16, 0x00100000, "RO", "page 32",
0x08, "Base Class Code", 8, "Subclass Code", 8, "Programming Interface", 8, "Revision ID", 8, 0x06000000, "RO", "page 32",
0x0C, "BIST", 8, "Header Type", 8, "Latency Timer", 8, "Cache Line Size", 8, 0x00800000, "RO", "page 33",
0x10, "Base Address 0", 32,                                  0x00000000, "RO", "",
0x14, "Base Address 1", 32, 0x00000000, "RO", "",
0x18, "Base Address 2", 32, 0x00000000, "RO", "",
0x1C, "Base Address 3", 32, 0x00000000, "RO", "",
0x20, "Base Address 4", 32, 0x00000000, "RO", "",
0x24, "Base Address 5", 32, 0x00000000, "RO", "",
0x28, "Card Bus CIS Pointer", 32, 0x00000000, "RO", "",
0x2C, "Sub-System ID", 16, "Sub-System Vendor ID", 16,  0x00000000, "RO", "",
0x30, "ROM Base Address", 32, 0x00000000, "RO", "",
0x34, "Capabilities", 32, 0x00000000, "RO", "",
0x38, "reserved", 32, 0x00000000, "RO", "",
0x3C, "Max Latency", 8, "Min GNT", 8, "Int Pin", 8, "Int Line", 8, 0x00000000, "RO", "",

0x40, "MCA Northbridge Control", 0, "reserved", 19,
"Watchdog Timer Error Reporting Enable", 1,
"Atomic Read-Modify-Write Error Reporting Enable", 1,
"GART Table Walk Error Reporting Enable", 1,
"Target Abort Error Reporting Enable", 1,
"Master Abort Error Reporting Enable", 1,
"HyperTransport Link 2 Sync Packet Error Reporting Enable", 1,
"HyperTransport Link 1 Sync Packet Error Reporting Enable", 1,
"HyperTransport Link 0 Sync Packet Error Reporting Enable", 1,
"HyperTransport Link 2 CRC Error Reporting Enable", 1,
"HyperTransport Link 1 CRC Error Reporting Enable", 1,
"HyperTransport Link 0 CRC Error Reporting Enable", 1,
"Uncorrectable ECC Error Reporting Enable", 1,
"Correctable ECC Error Reporting Enable", 1,
                    0x00000000, "RW", "page 96",
0x44, "MCA Northbridge Configuration", 0, "reserved", 6,

"PCI configuration CPU Error Response Disable", 1,
"I/O Read Data Error Log Enable", 1,
"Chip-Kill ECC Mode Enable", 1,
"ECC Enable", 1,
"Sync Flood On Any Error Enable", 1,
"Sync Flood on Watchdog Timer Error Enable", 1,
"reserved", 2,
"Generate CRC Error on Byte Lane 1", 1,
"Generate CRC Error on Byte Lane 0", 1,
"HyperTransport Link Select for CRC Error Generation", 2,
"Watchdog Timer Time Base Select", 2,
"Watchdog Timer Count Select", 3,
"Watchdog Timer Disable", 1,
"I/O Error Response Disable", 1,
"CPU Error Response Disable", 1,
"I/O Master Abort Error Response Disable", 1,
"Sync Packet Propagation Disable", 1,
"Sync Packet Generation Disable", 1,
"Sync Flood on Uncorrectable ECC Error Enable", 1,
"CPU Read Data Error Log Enable", 1,
"CPU ECC Error Log Enable", 1,
               0x00000000, "RW", "page 96",
0x48, "MCA Northbridge Status Low", 0, "Syndrome Bits 15-8 for Chip Kill ECC Mode", 8, "reserved", 4, "Extended Error Code", 4, "Error Code", 16,                 "",   "RW", "page 102",
0x4C, "MCA Northbridge Status High", 0,
"Error Valid", 1,
"Error Overflow", 1,
"Error Uncorrected", 1,
"Error Enable", 1,
"Miscellaneous Error Register Valid  R", 1,
"Error Address Valid", 1,
"Processor Context Corrupt", 1,
"reserved", 2,
"Syndrome Bits (7-0) for ECC Errors", 8,
"Correctable ECC Error", 1,
"Uncorrectable ECC Error", 1,
"reserved", 4,
"Error Found by DRAM Scrubber", 1,
"reserved", 1,
"HyperTransport Link Number", 3,
"reserved", 2,
"Error Associated with CPU 1", 1,
"Error Associated with CPU 0", 1,
                "",   "RW", "page 104",
0x50, "MCA Northbridge Address Low", 32,                 "",   "RW", "page 107",
0x54, "MCA Northbridge Address High", 32,                "",   "RW", "page 108",
0x58, "Scrub Control", 0, "reserved", 11, "Data Cache Scrub Rate", 5, "reserved", 3, "L2 Cache Scrub Rate", 5, "reserved", 3, "DRAM Scrub Rate", 5,                              0x00000000, "RW", "page 114",
0x5C, "DRAM Scrub Address Low", 31, "DRAM Scrubber Redirect Enable", 1,     "",   "RW", "page 116",
0x60, "DRAM Scrub Address High", 32,                     "",   "RW", "page 117",
0x70, "SRI-to-XBAR Buffer Counts", 32,                   0x51020111, "RW", "page 120",
0x74, "XBAR-to-SRI Buffer Counts", 32,                   0x50008011, "RW", "page 122",
0x78, "MCT-to-XBAR Buffer Counts", 32,                   0x08003800, "RW", "page 121",
0x7C, "Free List Buffer Counts", 32,                     0x0000221B, "RW", "page 122",
0x80, "Power Management Control Low", 32,                0x00000000, "RW", "page 125",
0x84, "Power Management Control High", 32,               0x00000000, "RW", "page 126",
0x90, "GART Aperture Control", 32,                       0x00000000, "RW", "page 127",
0x94, "GART Aperture Base", 32,                          "",   "RW", "page 128",
0x98, "GART Table Base", 32,                             "",   "RW", "page 129",
0x9C, "GART Cache Control", 32,                          0x00000000, "RW", "page 129",
0xD4, "Clock Power/Timing Low", 32,                      "",   "RW", "page 130",
0xD8, "Clock Power/Timing High", 32,                     "",   "RW", "page 132",
0xDC, "HyperTransport TM Read Pointer Optimization", 32,  "",  "RW", "page 132",

0xE4, "Thermtrip Status", 0,
"Software Thermtrip", 1,
"reserved", 17,
"Diode Offset", 6,
"reserved", 2,
"Thermtrip Enabled", 1,
"reserved", 1,
"Thermtrip Sense", 1,
"reserved", 1,
"Thermtrip", 1,
"reserved", 1,
          0x00000000, "RO", "page 134",
0xE8, "Northbridge Capabilities", 0,
"reserved", 23,
"Memory Controller Capable", 1,
"reserved", 1,
"Maximum DRAM Frequency", 2,
"Chip-Kill ECC Capable", 1,
"ECC Capable", 1,
"Big MP Capable", 1,
"MP Capable", 1,
"128-Bit DRAM Capable", 1,
 0x00000000, "RO", "page 135",

);

my %values = (
"Maximum DRAM Frequency" => [ "No limit", "166 MHz", "133 MHz", "100 MHz" ],
);

my @eccsyn = (

#Table 27.   ECC Syndromes
#   n=0      n=1      n=2    n=3    n=4    n=5    n=6    n=7
# Bit (0+n) 
   0xce,    0xcb,    0xd3,  0xd5,  0xd6,  0xd9,  0xda,  0xdc,
# Bit (8+n) 
   0x23,    0x25,    0x26,  0x29,  0x2a,  0x2c,  0x31,  0x34,
# Bit (16+n)
   0x0e,    0x0b,    0x13,  0x15,  0x16,  0x19,  0x1a,  0x1c,
# Bit (24+n)
   0xe3,    0xe5,    0xe6,  0xe9,  0xea,  0xec,  0xf1,  0xf4,
# Bit (32+n)
   0x4f,    0x4a,    0x52,  0x54,  0x57,  0x58,  0x5b,  0x5d,
# Bit (40+n)
   0xa2,    0xa4,    0xa7,  0xa8,  0xab,  0xad,  0xb0,  0xb5,
# Bit (48+n)
   0x8f,    0x8a,    0x92,  0x94,  0x97,  0x98,  0x9b,  0x9d,
# Bit (56+n)
   0x62,    0x64,    0x67,  0x68,  0x6b,  0x6d,  0x70,  0x75,
# Bit (64+n)
   0x01,    0x02,    0x04,  0x08,  0x10,  0x20,  0x40,  0x80,

	   );

my @chipkillsyn = (

#Table 28.    Chip Kill ECC Syndromes
# Symbol
#      1h      2h      3h      4h      5h      6h      7h      8h      9h      ah      bh      ch      dh      eh      fh
#   00h
   0xe821, 0x7c32, 0x9413, 0xbb44, 0x5365, 0xc776, 0x2f57, 0xdd88, 0x35a9, 0xa1ba, 0x499b, 0x66cc, 0x8eed, 0x1afe, 0xf2df,
#   01h
   0x5d31, 0xa612, 0xfb23, 0x9584, 0xc8b5, 0x3396, 0x6ea7, 0xeac8, 0xb7f9, 0x4cda, 0x11eb, 0x7f4c, 0x227d, 0xd95e, 0x846f,
#   02h
   0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007, 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
#   03h
   0x2021, 0x3032, 0x1013, 0x4044, 0x6065, 0x7076, 0x5057, 0x8088, 0xa0a9, 0xb0ba, 0x909b, 0xc0cc, 0xe0ed, 0xf0fe, 0xd0df,
#   04h
   0x5041, 0xa082, 0xf0c3, 0x9054, 0xc015, 0x30d6, 0x6097, 0xe0a8, 0xb0e9, 0x402a, 0x106b, 0x70fc, 0x20bd, 0xd07e, 0x803f,
#   05h
   0xbe21, 0xd732, 0x6913, 0x2144, 0x9f65, 0xf676, 0x4857, 0x3288, 0x8ca9, 0xe5ba, 0x5b9b, 0x13cc, 0xaded, 0xc4fe, 0x7adf,
#   06h
   0x4951, 0x8ea2, 0xc7f3, 0x5394, 0x1ac5, 0xdd36, 0x9467, 0xa1e8, 0xe8b9, 0x2f4a, 0x661b, 0xf27c, 0xbb2d, 0x7cde, 0x358f,
#   07h
   0x74e1, 0x9872, 0xec93, 0xd6b4, 0xa255, 0x4ec6, 0x3a27, 0x6bd8, 0x1f39, 0xf3aa, 0x874b, 0xbd6c, 0xc98d, 0x251e, 0x51ff,
#   08h
   0x15c1, 0x2a42, 0x3f83, 0xcef4, 0xdb35, 0xe4b6, 0xf177, 0x4758, 0x5299, 0x6d1a, 0x78db, 0x89ac, 0x9c6d, 0xa3ee, 0xb62f,
#   09h
   0x3d01, 0x1602, 0x2b03, 0x8504, 0xb805, 0x9306, 0xae07, 0xca08, 0xf709, 0xdc0a, 0xe10b, 0x4f0c, 0x720d, 0x590e, 0x640f,
#   0ah
   0x9801, 0xec02, 0x7403, 0x6b04, 0xf305, 0x8706, 0x1f07, 0xbd08, 0x2509, 0x510a, 0xc90b, 0xd60c, 0x4e0d, 0x3a0e, 0xa20f,
#   0bh
   0xd131, 0x6212, 0xb323, 0x3884, 0xe9b5, 0x5a96, 0x8ba7, 0x1cc8, 0xcdf9, 0x7eda, 0xafeb, 0x244c, 0xf57d, 0x465e, 0x976f,
#   0ch
   0xe1d1, 0x7262, 0x93b3, 0xb834, 0x59e5, 0xca56, 0x2b87, 0xdc18, 0x3dc9, 0xae7a, 0x4fab, 0x642c, 0x85fd, 0x164e, 0xf79f,
#   0dh
   0x6051, 0xb0a2, 0xd0f3, 0x1094, 0x70c5, 0xa036, 0xc067, 0x20e8, 0x40b9, 0x904a, 0xf01b, 0x307c, 0x502d, 0x80de, 0xe08f,
#   0eh
   0xa4c1, 0xf842, 0x5c83, 0xe6f4, 0x4235, 0x1eb6, 0xba77, 0x7b58, 0xdf99, 0x831a, 0x27db, 0x9dac, 0x396d, 0x65ee, 0xc12f,
#   0fh
   0x11c1, 0x2242, 0x3383, 0xc8f4, 0xd935, 0xeab6, 0xfb77, 0x4c58, 0x5d99, 0x6e1a, 0x7fdb, 0x84ac, 0x956d, 0xa6ee, 0xb72f,
#   10h
   0x45d1, 0x8a62, 0xcfb3, 0x5e34, 0x1be5, 0xd456, 0x9187, 0xa718, 0xe2c9, 0x2d7a, 0x68ab, 0xf92c, 0xbcfd, 0x734e, 0x369f,
#   11h
   0x63e1, 0xb172, 0xd293, 0x14b4, 0x7755, 0xa5c6, 0xc627, 0x28d8, 0x4b39, 0x99aa, 0xfa4b, 0x3c6c, 0x5f8d, 0x8d1e, 0xeeff,
#   12h
   0xb741, 0xd982, 0x6ec3, 0x2254, 0x9515, 0xfbd6, 0x4c97, 0x33a8, 0x84e9, 0xea2a, 0x5d6b, 0x11fc, 0xa6bd, 0xc87e, 0x7f3f,
#   13h
   0xdd41, 0x6682, 0xbbc3, 0x3554, 0xe815, 0x53d6, 0x8e97, 0x1aa8, 0xc7e9, 0x7c2a, 0xa16b, 0x2ffc, 0xf2bd, 0x497e, 0x943f,
#   14h
   0x2bd1, 0x3d62, 0x16b3, 0x4f34, 0x64e5, 0x7256, 0x5987, 0x8518, 0xaec9, 0xb87a, 0x93ab, 0xca2c, 0xe1fd, 0xf74e, 0xdc9f,
#   15h
   0x83c1, 0xc142, 0x4283, 0xa4f4, 0x2735, 0x65b6, 0xe677, 0xf858, 0x7b99, 0x391a, 0xbadb, 0x5cac, 0xdf6d, 0x9dee, 0x1e2f,
#   16h
   0x8fd1, 0xc562, 0x4ab3, 0xa934, 0x26e5, 0x6c56, 0xe387, 0xfe18, 0x71c9, 0x3b7a, 0xb4ab, 0x572c, 0xd8fd, 0x924e, 0x1d9f,
#   17h
   0x4791, 0x89e2, 0xce73, 0x5264, 0x15f5, 0xdb86, 0x9c17, 0xa3b8, 0xe429, 0x2a5a, 0x6dcb, 0xf1dc, 0xb64d, 0x783e, 0x3faf,
#   18h
   0x5781, 0xa9c2, 0xfe43, 0x92a4, 0xc525, 0x3b66, 0x6ce7, 0xe3f8, 0xb479, 0x4a3a, 0x1dbb, 0x715c, 0x26dd, 0xd89e, 0x8f1f,
#   19h
   0xbf41, 0xd582, 0x6ac3, 0x2954, 0x9615, 0xfcd6, 0x4397, 0x3ea8, 0x81e9, 0xeb2a, 0x546b, 0x17fc, 0xa8bd, 0xc27e, 0x7d3f,
#   1ah
   0x9391, 0xe1e2, 0x7273, 0x6464, 0xf7f5, 0x8586, 0x1617, 0xb8b8, 0x2b29, 0x595a, 0xcacb, 0xdcdc, 0x4f4d, 0x3d3e, 0xaeaf,
#   1bh
   0xcce1, 0x4472, 0x8893, 0xfdb4, 0x3155, 0xb9c6, 0x7527, 0x56d8, 0x9a39, 0x12aa, 0xde4b, 0xab6c, 0x678d, 0xef1e, 0x23ff,
#   1ch
   0xa761, 0xf9b2, 0x5ed3, 0xe214, 0x4575, 0x1ba6, 0xbcc7, 0x7328, 0xd449, 0x8a9a, 0x2dfb, 0x913c, 0x365d, 0x688e, 0xcfef,
#   1dh
   0xff61, 0x55b2, 0xaad3, 0x7914, 0x8675, 0x2ca6, 0xd3c7, 0x9e28, 0x6149, 0xcb9a, 0x34fb, 0xe73c, 0x185d, 0xb28e, 0x4def,
#   1eh
   0x5451, 0xa8a2, 0xfcf3, 0x9694, 0xc2c5, 0x3e36, 0x6a67, 0xebe8, 0xbfb9, 0x434a, 0x171b, 0x7d7c, 0x292d, 0xd5de, 0x818f,
#   1fh
   0x6fc1, 0xb542, 0xda83, 0x19f4, 0x7635, 0xacb6, 0xc377, 0x2e58, 0x4199, 0x9b1a, 0xf4db, 0x37ac, 0x586d, 0x82ee, 0xed2f,
#   20h
   0xbe01, 0xd702, 0x6903, 0x2104, 0x9f05, 0xf606, 0x4807, 0x3208, 0x8c09, 0xe50a, 0x5b0b, 0x130c, 0xad0d, 0xc40e, 0x7a0f,
#   21h
   0x4101, 0x8202, 0xc303, 0x5804, 0x1905, 0xda06, 0x9b07, 0xac08, 0xed09, 0x2e0a, 0x6f0b, 0xf40c, 0xb50d, 0x760e, 0x370f,
#   22h
   0xc441, 0x4882, 0x8cc3, 0xf654, 0x3215, 0xbed6, 0x7a97, 0x5ba8, 0x9fe9, 0x132a, 0xd76b, 0xadfc, 0x69bd, 0xe57e, 0x213f,
#   23h
   0x7621, 0x9b32, 0xed13, 0xda44, 0xac65, 0x4176, 0x3757, 0x6f88, 0x19a9, 0xf4ba, 0x829b, 0xb5cc, 0xc3ed, 0x2efe, 0x58df,

		);

$ENV{'PATH'} .= ":/sbin:/usr/sbin:/usr/local/sbin";

# Ok, that's the tables, now the code.

for (my $cpu = 0; ; ++$cpu) {
    # Test for existence
    my $s = sprintf ("00:%02X.%d", 0x18+$cpu, 0);
    my $v = `setpci -s $s 00.L 2>/dev/null`;
    #print "DO: setpci -s $s 00.L 2>/dev/null\n";
    #print "GET: '$v'\n";
    chomp ($v);
    last if $v eq '';

    my $function = -1;
    my $prevaddr = 10000;
    my @r = @regs;
    while (scalar @r) {
	my $addr = shift @r;
	if ($addr < $prevaddr) {
	    $function ++;
	    print "\nFunction $function:\n\n";
	}
	$prevaddr = $addr;

	my $s = sprintf ("00:%02X.%d", 0x18+$cpu, $function);
	my $a = sprintf ("%02X", $addr);
	my $v = `setpci -s $s $a.L 2>/dev/null`;
	chomp ($v);
	die "Address: $s $a.L: Invalid value: '$v'\n" unless $v =~ /^[0-9a-f]{8}$/i;
	$v = hex($v);
	printf ("%s %s.L: 0x%08X\n", $s, $a, $v);

	# Loop on values.  Run until bits left == 0.

	for (my $bit = 0; $bit < 32; ) {
	    my $txt = shift @r;
	    my $l = shift @r;
	    if ($l !~ /^[0-9]+$/ || $l + $bit > 32) {
		die "Address: $s $a.L: Invalid bit count: $l, pos $bit";
	    }
	    $bit += $l;
	    if ($txt eq 'reserved') {
		# print nothing
	    } elsif ($l == 0) {
		print "    $txt\n";
	    } else {
		my $v2 = ($v >> (32 - $bit)) & (0xffffffff >> (32 - $l));
		if (defined $values{$txt}) {
		    print "\t$txt ($bit,$l): " . $values{$txt}->[$v2] . "\n";
		} elsif ($v2 < 10) {
		    printf ("\t$txt ($bit,$l): %d\n", $v2);
		} else {
		    my $hexw = int(($l+3)/4);
		    printf ("\t$txt ($bit,$l): %d 0x%0*X\n", $v2, $hexw, $v2);
		}
	    }
	}

	# Then shift away default values, RW/RO status and manual page reference.
	my $default = shift @r;
	my $rw = shift @r;
	my $page = shift @r;
    }
}